ecn: s-00164erev. f, 31-jan-00 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all leads q 0.101 mm 0.004o l ba 1 a e d 0.25 (gage plane) figure 1. little foot package dimensions AN801 vishay siliconix document number: 70591 06-jun-00 www.vishay.com faxback 408-970-5600 1 designing with little foot power mosfets in surface-mount (so-8) packages vishay siliconix' little foot power mosfets pack potent power handling into tiny surface-mount packages. the standard-outline, 8-pin soic package (figure 1) has a copper leadframe that maximizes thermal transfer while maintaining complete compatibility with existing surface-mount technology. the complementary n- and p-channel si9942dy little foot device can be used to drive inductive loads such as motors, solenoids, and relays directly, or as a low-impedance buffer to drive larger power mosfets or other capacitive loads. little foot devices offer measurable advantages in a variety of low-voltage motor drive applications. in a computer hard disk, key features such as track density, seek time, and power consumption are directly related to the efficiency of the spindle motor and the head actuator drive circuitry. disk drives must squeeze maximum motor performance from low-voltage supplies (traditionally, well-regulated 12-v supplies) provided by the computer system. the advent of sophisticated full-function portable computers brings new performance expectations of battery driven systems (and 5-v operation). for 12-v battery powered applications, designers must strive to limit voltage dropsewhich waste motor drive voltage, reduce battery life, and contribute heat that must be dissipated, often at considerable expense. little foot devices such as the complementary n- and p-channel si9942dy substantially increase the motor size that can be driven from surface-mount power devices without additional heatsinking. the si9942dy can also be used in power conversion applications as a buffer stage to drive highly capacitive power mosfet gates at the high frequencies used in modern designs. for example, by using an si9942dy to buffer the output of highly efficient cmos pwm controllers, capacitive loads in excess of 3000 pf can be efficiently switched at rates greater than 1 mhz. this switching ability greatly extends the output power range of cmos switchmode ics. this application note describes the basic mosfet parameters that are important when driving inductive and capacitive loads and shows characteristics of the si9942dy.
dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q 0 8 0 8
AN801 vishay siliconix www.vishay.com faxback 408-970-5600 2 document number: 70591 06-jun-00 driving inductive loads when driving inductive loads with power mosfets, several parameters that might otherwise be of secondary concern become very important. one characteristic of inductive loads is flyback energy. when inductor drive current is interrupted, damaging flyback voltages can result unless diodes are used to clamp the voltage and allow the inductive flyback current to freewheel. each power mosfet contains a fast-recovery intrinsic diode that can be used as a reliable and efficient clamp for inductive flyback energy. of particular importance in the use of the mosfet's reverse characteristics are its intrinsic diode specificationsev sd (reverse source-drain voltage, which is the diode forward voltage drop) and t rr (reverse-recovery time). the flyback current recirculating through the diode clamps is equal to the motor current, which reaches its maximum level during motor acceleration or braking. although power lost in the clamp diodes (v sd times the recirculation current) occupies a small percentage of the duty cycle, it can contribute significantly to overall mosfet heating if the forward voltage drop is excessive. both the n-channel and p-channel devices of each half-bridge are specified with a maximum forward voltage drop of 1.6 v at the mosfets' maximum (continuous) forward drain current rating. the intrinsic diode t rr becomes important any time the motor current is interrupted by turning off the mosfet switches. when drive is re-enabled in the same path, while flyback current is still recirculating in the opposing clamp diodes, recombination will have to occur before the diode recovers and blocks voltage (figure 2). figure 3 illustrates the relationship of the diode reverse-recovery characteristics with gate drive impedance. the load inductance is shown referenced to v+, and the upper mosfet's gate is shorted to the source to isolate its intrinsic diode for demonstration purposes. during time t1, the lower mosfet (q1) is turned on and load current is conducted through the inductor to ground. at the leading edge of time t2, q1 is turned off and flyback current from the inductor recirculates through the intrinsic diode in mosfet q2. shoot-through current occurs during time t3, when q1 is switched back on. as q1 is turned back on, it conducts current from both the load and reverse current through the diode of q2, which has yet to recover. when enough current is conducted to reverse the voltage potential across the diode of q2, it begins to recover. duration of the current spike is dependent on the power mosfet t rr (a function of the diode's forward current and forced recovery di/dt). the current spike magnitude depends on the product of the gate voltage and the g fs of q1 at the time of q2's diode recovery (figure 3a). figure 2. clamping inductive flyback energy motor drive v+ (t1) q1 on q2 off q4 off q3 on d1 d2 d3 d4 (t1) q1 and q3 on for motor drive. inductive flyback v+ (t2) q1 off q2 off q4 off q3 off d1 d2 d3 d4 (t2) power mosfets off, inductor fly- back is conducted through diodes d2 and d4. motor drive (re-enabled) v+ (t3) q1 on q2 off q4 off q3 on d1 d2 d3 d4 (t3) if q1 or q3 are turned on before the flyback energy is fully dissipated, a current path will exist between the power supply and the ground during the diode t rr . the amount of shoot-through current that results depends on series gate drive impedance (how fast the opposing little foot device is turned on), stray series inductance, and diode reverse recovery time.
AN801 vishay siliconix document number: 70591 06-jun-00 www.vishay.com faxback 408-970-5600 3 figure 3. shoot-through current and dv/dt vs. gate drive impedance v gs (q1) v th v sd (q1) i d (q1) t1 t2 t3 t4 t rr (q1) v th v+ a b c a b c v gs (q1) v th v sd (q1) i d (q1) t1 t2 t3 t4 t rr (q1) v th v+ a b c t1 and t4 t2 t3 q1 q2 v+ 3a) 3b) a b c t1 and t4 t2 t3 q1 q2 v+ as the value of gate drive resistance (r1) is increased, the turn-on rate of q1 (during time t3) is reduced (figure 3b). by reducing the rate of gate drive voltage rise (dv gs /dt), the level of gate voltage present when the diode recovers is reduced, thereby reducing the peak shoot-through current level. as gate drive impedance r1 is increased, the forced recovery current rate (di/dt) is also reduced, which actually increases t rr in mosfet q2's diode. (the total amount of charge which must recombine remains the same regardless of di/dt, and since the maximum current level is now restricted, time is increased.) efficiency is not increased by reducing peak shoot-through current, however, potentially damaging levels of peak current will be avoided, and emi/rfi will be reduced. determining the proper gate drive impedance to achieve the desired reverse-recovery characteristics and system emi/rfi requirements must be balanced against the maximum transition times required to achieve acceptable switching losses. as a basis for understanding the impact of switching time and the resulting switching losses on overall system efficiency, we must assume some typical operating conditions. if the modulation frequency is 20 khz, one cycle will be 50 s. if the transition time objectives are arbitrarily set at 1% of the overall duty cycle duration (500 ns total), each transition (including worst-case t rr ) must be less than 250 ns. the oscilloscope photograph (figure 4a) demonstrates that this is a reasonable goal. these transition waveforms result when the configuration shown in figure 4 is driven directly by a cmos logic gate. the oscilloscope photograph in figure 4b illustrates the output current and voltage waveforms with a 500- series gate resistor (r1). in both examples, figures 4a and 4b, a cd4000 series cmos logic device was used to drive the power mosfet gate.
AN801 vishay siliconix www.vishay.com faxback 408-970-5600 4 document number: 70591 06-jun-00 figure 4. cmos gate drive and resulting output waveforms (si9942) a b r1 v+ motor winding 2 v 2 v 50 ns 2 v 2 v 50 ns a a b b 4a 4b aside from the obvious reasons for limiting di/dt during t rr , extreme rates of dv ds /dt can result at the end of time t3 (figures 3a and 3b). this recovery dv ds /dt (commutating dv/dt) is primarily a function of the di/dt and peak shoot-through current forced during the diode recovery time. all power mosfets have some sensitivity to commutating dv/dt; figure 5 indicates what characterization data has shown to be asafeo dv/dt rates as a function of forward diode current prior to a forced recovery. this applies only if the forced voltage across the device (v+ or v battery ) is above 85% of the v (br)dss . for modern dmos geometries, commutating dv/dt sensitivity decreases drastically and ceases to have any effect below approximately 60% of the v (br)dss rating. figure 5. reverse-recovery dv ds /dt sensitivity 0 100% 200% 300% 5 10 0 slew rate dv/dt v/ns di/dt = 100 a/ s percent of rated commutation current
AN801 vishay siliconix document number: 70591 06-jun-00 www.vishay.com faxback 408-970-5600 5 common gate drive a common cause of simultaneous conduction results from connecting the p-channel and n-channel gates together and driving them from a common logic signal. while this may be a completely acceptable gate drive method for capacitive loads or for lower voltage systems, it will probably result in excessive crossover current when driving inductive loads with 12 v across the bridge. if the gates are driven in common, the correct output states will result; however, this occurs at the expense of a current spike caused by both devices being partially turned on as the common gate voltage is in transition between approximately 2 v (n-channel threshold voltage) and 8 v (12 v minus p-channel threshold voltage). figure 6. crossover current caused by common gate drive +12 v v in i cc v in i sd 100 s si9942dy 2 v 1 a figure 6 demonstrates the crossover current that can exist in the si9942dy at v+ = +12 v with the gates driven by a ramp voltage. in this example, the crossover current reached a peak of 3 a, limited only by the g fs of each device (with limited enhancement voltage above the threshold voltage) and by the series resistance. figure 7. complementary buffer stage with shoot-through current limiting +12 v r1 v in i cc v in i sd si9942dy 2 v 50 ma 100 s in figure 7, a pre-driver stage has been added that virtually eliminates crossover current under these same conditions. the impedance of the p-channel and n-channel buffer stage governs the turn-off times of the output devices. and r1, plus the buffer mosfet's on-resistance, sets the turn-on times. as will be discussed under adriving capacitive loads,o it may be perfectly acceptable to tie the gates together when driving capacitive loads. disk drive applications using dual mosfets with p-channel and n-channel devices allows the simplest gate drive circuitry to be used, since both gates can be pulled to ground or to the 12-v supply. the half-bridge used to drive each phase of the spindle motor (figure 8) or head actuator (figure 9) is typically driven directly by the output of a standard cmos logic device powered from the same 12-v supply. while the relatively high output impedance of a cmos logic device will not drive the capacitive gates of the half-bridge hard enough to attain maximum switching speeds, the combination will provide sufficiently fast transition rates to result in tolerable switching losses. driving the power mosfet gates with lower impedance drivers will result in faster transition rates and further reduce switching losses; however, the designer is usually forced to strike a balance between switching losses and increased emi/rfi. this is of particular concern in rotating disk drive memories.
AN801 vishay siliconix www.vishay.com faxback 408-970-5600 6 document number: 70591 06-jun-00 figure 8. 12-v, 3-phase permanent magnet brushless motor drive +12 v cmos controller 3-phase brushless dc spindle motor si9942dy si9942dy figure 9. 12-v h-bridge actuator drive +12 v head actuator the 12-v supply provided to the peripheral function by the host computer system is usually clean and regulated to 10%. one of the designer's greatest tasks is to achieve the desired motor drive performance without destroying the supply's integrity. this is accomplished by managing a number of trade-offs, such as the balance previously noted between transition rates and emi. another prime concern is any shoot-through current caused by the simultaneous conduction of both devices in one half-bridge. one common cause of this condition is the reverse conduction of current through the body-drain diode during the diode t rr , as previously discussed.
AN801 vishay siliconix document number: 70591 06-jun-00 www.vishay.com faxback 408-970-5600 7 driving capacitive loads highly efficient cmos devices are a natural complement to the low-loss power handling capabilities of power mosfets. however, cmos outputs are relatively high impedance and power mosfet gates are highly capacitive. if high frequencies are necessary, some type of gate drive buffer must be used. the si9942dy will function perfectly in this application as a very low-impedance, complementary output stage for the cmos device. the gate capacitances are easily driven by standard cmos outputs, and the single-stage, complementary pair adds minimal delay. the high-efficiency cmos current-mode regulator illustrated in figure 10 demonstrates a combination that takes advantage of the characteristics of each device. the vishay siliconix si9100 series of current-mode controller ics, built with cmos/dmos (power ic) technology, includes regulators and controllers. the regulators feature an on-board output power device, and the controllers have a cmos output designed to drive an external power mosfet with higher current or voltage capability. this cmos output is capable of driving power mosfets up to 1000 pf (c iss ) at the 500-khz maximum switching frequency. in the oscilloscope photograph in figure 10, voltage waveforms demonstrate the rise and fall times attained at the common gates of the si9942dy (trace a) and the gate of the smw14n50f output device used in this example (trace b). symmetrical rise and fall times of less than 10 ns are sufficient to provide minimal transition losses, even at 500 khz. with a capacitive load (figure 11), the gates of the p-channel and n-channel complementary stage devices can usually be tied together and driven in common without the penalty of cross-conduction current that could be present with an inductive load. as discussed in the adriving inductive loadso section, with 12 v across the complementary stage, both devices will be partially on as the gates' transition between about 2 and 8 v. but with the capacitive load representing an essentially vertical load line during the first few nanoseconds of the transition, dv gs /dt usually exceeds dv ds /dt, and what would have been cross-conduction current goes into charging the load. figure 10. very low-impedance power mosfet gate driver v+ ref error amp osc & ramp gen pwm output buffer low voltage reg v dd +12 v si9942dy a b trace b trace a 5 v 50 ns 5 v controller
AN801 vishay siliconix www.vishay.com faxback 408-970-5600 8 document number: 70591 06-jun-00 figure 11. common gate drive with capacitive loads si9942dy cd4000 +12 v v in i sd 2 v 50 ma 100 s summary the si9942dy combines p-channel and n-channel half-bridge architecture with the high-impedance gate characteristics of power mosfets, making the device extremely easy and efficient to drive. rugged little foot devices are designed to provide reliable, optimized performance for inductive loads such as motors, actuators, and solenoids. the power mosfets' intrinsic diodes are designed and specified to function reliably and efficiently as clamp diodes when driving inductive loads. the si9942dy can also serve as a very low-impedance output buffer stage to extend the range of capacitive loads driven by cmos circuitry. the p-channel and n-channel half-bridge configuration allows the two gates to be tied together and driven directly by a common cmos output in low-voltage applications. the single complementary stage offers minimum propagation delay and very low-impedance output, which greatly extends the output power range of high-frequency cmos controllers.
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